Digi NS9750 User Manual

NS9750B-A1 DatasheetThe Digi NS9750B-A1 is a single chip 0.13μm CMOS network-attached processor. The CPU is the ARM926EJ-S core with MMU, DSP extensio

System configuration6       NS9750B-A1 Datasheet 03/2006gpio[19] RESERVED. This pin must not be pulled to logic 0 until reset_done is a logic

General Purpose ID registerwww.digi.com       7General Purpose ID registerThere are 32 additional GPIO pins that are used to create a general p

System boot8       NS9750B-A1 Datasheet 03/2006System bootThere are two ways to boot the NS9750B-A1 system: From a fast Flash over the syste

System Clockwww.digi.com       94 The memory controller settings are read from the serial EEPROM and used to initialize the memory controller.

System Clock10       NS9750B-A1 Datasheet 03/2006Figure 2: NS9750B-A1 system clockThe PLL parameters are initialized on powerup reset and can

USB clockwww.digi.com       11USB clockUSB is clocked by a separate PLL driven by an external 48 MHz crystal, or it can be driven directly by a

NS9750B-A1 pinout and signal descriptions12       NS9750B-A1 Datasheet 03/2006NS9750B-A1 pinout and signal descriptionsEach pinout table appl

System Memory interfacewww.digi.com       13C15 addr[12] 8 O Address bus signalB15 addr[13] 8 O Address bus signalA15 addr[14] 8 O Address bus

System Memory interface14       NS9750B-A1 Datasheet 03/2006F24 data[7] 8 I/O Data bus signalE25 data[8] 8 I/O Data bus signalD26 data[9] 8 I

System Memory interfacewww.digi.com       15F4 byte_lane_sel_n[1] 8 O Static memory byte_lane_enable[1] or write_enable_n[1] for byte-wide devi

features a PCI/CardBus port as well as a USB port for applications that require WLAN, external storage, or external sensors, imagers, or scanners. Fou

System Memory interface signals16       NS9750B-A1 Datasheet 03/2006System Memory interface signalsTable 6 describes the System Memory interf

System Memory interface signalswww.digi.com       17Figure 4 shows NS9750B-A1 SDRAM clock termination.Figure 4: SDRAM clock terminationC3clk_in

Ethernet interface18       NS9750B-A1 Datasheet 03/2006Ethernet interfacePin #Signal nameU/DOD(mA)I/ODescriptionMII RMII MII RMIIAB1 col N/C

Clock generation/system pinswww.digi.com       19Clock generation/system pinsPin # Signal nameU/DOD(mA)I/O DescriptionC8 x1_sys_osc I System cl

bist_en_n, pll_test_n, and scan_en_n20       NS9750B-A1 Datasheet 03/2006bist_en_n, pll_test_n, and scan_en_nTable 9 is a truth/termination t

PCI interfacewww.digi.com       21U24 ad[16]1N/A I/O PCI time-multiplexed address/data busV26 ad[17]1N/A I/O PCI time-multiplexed address/data

PCI/CardBus signals22       NS9750B-A1 Datasheet 03/2006PCI/CardBus signalsMost of the CardBus signals are the same as the PCI signals. Other

PCI/CardBus signalswww.digi.com       23Notes:1 Add external pulldown resistor or drive with the NS9750B-A1 only if the PCI interface is not be

PCI/CardBus signals24       NS9750B-A1 Datasheet 03/2006Figure 5 shows how to terminate an unused PCI.Notes: Startup code needs to put the P

GPIO MUXwww.digi.com       25GPIO MUX The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be selected individually;

ContentsiiiNS9750B-A1 Features... 1System-level interfaces ...

GPIO MUX26       NS9750B-A1 Datasheet 03/2006AD16 gpio[6] U 2 I/O 00 Ser port B RI / SPI port B clk01 1284 nFault (peripheral-driven)102 Tim

GPIO MUXwww.digi.com       27AD13 gpio[16]2U 2 I/O 00 Reserved output01 1284 nFault (peripheral-driven, duplicate)302 Timer 11 (duplicate) or U

GPIO MUX28       NS9750B-A1 Datasheet 03/2006AD10 gpio[26] U 4 I/O 00 Ser port D RI / SPI port D clk01 LCD data bit 202 Timer 303 GPIO 26AF9

GPIO MUXwww.digi.com       29AF5 gpio[36] U 4 I/O 00 Reserved01 1284 Data 5 (bidirectional)02 LCD data bit 1203 GPIO 36AD6 gpio[37] U 4 I/O 00

GPIO MUX30       NS9750B-A1 Datasheet 03/2006AB3 gpio[46] U 4 I/O 00 Ser port D RTS01 1284 nAutoFd (host-driven)02 LCD data bit 2203 GPIO 46

LCD module signalswww.digi.com       31Example: Implementing gpio[16] and gpio[17]LCD module signalsThe LCD module signals are multiplexed with

LCD module signals32       NS9750B-A1 Datasheet 03/2006The CLD[23:0] signal has eight modes of operation:Tabl e 1 4 s h ow s wh i ch CLD[23

LCD module signalswww.digi.com       33Tabl e 1 5 s h ow s wh i ch CLD[23:0] pins provide the pixel data to the TFT panel for each of the mul

LCD module signals34       NS9750B-A1 Datasheet 03/2006This LCD TFT panel signal multiplexing table shows the RGB alignment to a 15-bit TFT w

I2C interfacewww.digi.com       35I2C interfaceUSB InterfaceNotes: If not using the USB interface, these pins should be pulled down to ground

iv       NS9750B-A1 Datasheet 03/2006LCD timing ... 66SPI ti

JTAG interface for ARM core/boundary scan36       NS9750B-A1 Datasheet 03/2006JTAG interface for ARM core/boundary scanNote: trst_n must be p

Reserved pinswww.digi.com       37Reserved pinsPin# DescriptionJ1 Tie to ground directlyE2 Tie to ground directlyK3 Tie to ground directlyK2 Ti

Power ground38       NS9750B-A1 Datasheet 03/2006Power groundAddress and register mapsSystem address mapThe system memory address is divided

BBus peripheral address mapwww.digi.com       39BBus peripheral address mapThe BBus bridge configuration registers are located at base address

Electrical characteristics40       NS9750B-A1 Datasheet 03/2006Electrical characteristicsThe NS9750B-A1 operates at a 1.5V core, with 3.3V I/

Maximum power dissipationwww.digi.com       41Maximum power dissipationTable 24 shows the maximum power dissipation, including sleep mode infor

DC electrical characteristics42       NS9750B-A1 Datasheet 03/2006DC electrical characteristicsDC electrical characteristics specify the wors

Outputswww.digi.com       43OutputsAll electrical outputs are 3.3V interface.USB DC electrical outputsNotes:1 Measured with RL of 1.425k ohm to

Reset and edge sensitive input timing requirements44       NS9750B-A1 Datasheet 03/2006Reset and edge sensitive input timing requirementsThe

Power sequencingwww.digi.com       45Power sequencingUse these requirements for power sequencing.VDDU3RESET delay is determinedby capacitor on

NS9750B-A1 Featureswww.digi.com       1NS9750B-A1 Features32-bit ARM926EJ-S RISC processor 125 to 200 MHz 5-stage pipeline with interlocking

Memory timing46       NS9750B-A1 Datasheet 03/2006Memory timingMemory AC characteristics are measured with 35pF, unless otherwise noted.Memor

SDRAM timingwww.digi.com       47SDRAM burst read (16-bit)Notes:1 This is the bank and RAS address.2 This is the CAS addressSDRAM burst read (1

SDRAM timing48       NS9750B-A1 Datasheet 03/2006SDRAM burst write (16-bit)Notes:1 This is the bank and RAS address.2 This is the CAS address

SDRAM timingwww.digi.com       49SDRAM burst read (32-bit), CAS latency = 3Notes:1 This is the bank and RAS address.2 This is the CAS address.S

SDRAM timing50       NS9750B-A1 Datasheet 03/2006SDRAM load modeSDRAM refresh modeClock enable timingM4M9M8M7M5op codeclk_out<3:0>dy_cs

SRAM timingwww.digi.com       51SRAM timingTable 27 describes the values shown in the SRAM timing diagrams.Notes:1 Only one of the four dy_cs_n

SRAM timing52       NS9750B-A1 Datasheet 03/2006Static RAM read cycles with 0 wait states WTRD = 1WOEN = 1 If the PB field is set to 1, all

SRAM timingwww.digi.com       53Static RAM asynchronous page mode read, WTPG = 1 WTPG = 1WTRD = 2 If the PB field is set to 1, all four byte_

SRAM timing54       NS9750B-A1 Datasheet 03/2006Static RAM read cycle configurable wait states WTRD = from 1 to 15WOEN = from 0 to 15 If th

SRAM timingwww.digi.com       55Static RAM write cycle WTWR = 0WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low. Du

NS9750B-A1 Features2       NS9750B-A1 Datasheet 03/2006Flexible LCD controller Supports most commercially available displays:– Active Matrix

SRAM timing56       NS9750B-A1 Datasheet 03/2006Static write cycle with configurable wait states WTWR = from 0 to 15WWEN = from 0 to 15 The

Slow peripheral acknowledge timingwww.digi.com       57Slow peripheral acknowledge timingTable 28 describes the values shown in the slow periph

Slow peripheral acknowledge timing58       NS9750B-A1 Datasheet 03/2006Slow peripheral acknowledge readSlow peripheral acknowledge writeM32 M

Ethernet timingwww.digi.com       59Ethernet timingEthernet AC characteristics are measured with 10pF, unless otherwise noted.Table 29 describe

Ethernet timing60       NS9750B-A1 Datasheet 03/2006Ethernet MII timingEthernet RMII timingE6E5E4E3E2E1E7E7E13E12E11tx_clktxd[3:0],tx_en,tx_e

PCI timingwww.digi.com       61PCI timingPCI AC characteristics are measured with 10pF, unless otherwise noted.Table 30 and Table 31 describe t

PCI timing62       NS9750B-A1 Datasheet 03/2006Notes:1 Minimum times are specified with 0pf and maximum times are specified with 30pf.2 pci_c

PCI timingwww.digi.com       63PCI burst write from NS9750B-A1 timingNote:The functional timing for trdy_n and devsel_n shows the fastest possi

PCI timing64       NS9750B-A1 Datasheet 03/2006PCI burst write to NS9750B-A1 timingPCI burst read to NS9750B-A1 timingNote:The functional tim

I2C timingwww.digi.com       65I2C timingI2C AC characteristics are measured with 10pF, unless otherwise noted.Table 32 describes the values sh

NS9750B-A1 Featureswww.digi.com       3Peripheral bus: One 13-channel DMA engine supports USB device– 2 DMA channels support control endpoint–

LCD timing66       NS9750B-A1 Datasheet 03/2006LCD timingLCD AC characteristics are measured with 10pF, unless otherwise noted.Table 33 descr

LCD timingwww.digi.com       67Notes:1 CLCDCLK is selected from 5 possible sources:— lcdclk/2 (lcdclk is an external oscillator)— AHB clock— AH

LCD timing68       NS9750B-A1 Datasheet 03/2006Horizontal timing for STN displaysVertical timing for STN displaysHorizontal timing for TFT di

LCD timingwww.digi.com       69HSYNC vs VSYNC timing for STN displaysHSYNC vs VSYNC timing for TFT displaysLCD output timingL24L25L23L12CLFPCLL

SPI timing70       NS9750B-A1 Datasheet 03/2006SPI timingSPI AC characteristics are measured with 10pF, unless otherwise noted.Table 34 descr

SPI timingwww.digi.com       71Notes:1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel B/A/C/D Control R

SPI timing72       NS9750B-A1 Datasheet 03/2006SPI slave mode 0 and 1: 2-byte transfer (see note 7)SPI slave mode 2 and 3: 2-byte transfer (s

IEEE 1284 timingwww.digi.com       73IEEE 1284 timingIEEE 1284 AC characteristics are measured with 10pF, unless otherwise noted.Table 35 descr

USB timing74       NS9750B-A1 Datasheet 03/2006USB timingTable 36 and Table 37 describe the values shown in the USB timing diagrams.Notes:1 L

USB timingwww.digi.com       75USB full speed loadUSB low speed loadCL = 50pfRSusb_dpCL = 50pfRSusb_dmFull Speed BufferRs - external resistorCL

System-level interfaces4       NS9750B-A1 Datasheet 03/2006System-level interfacesFigure 1 shows the NS9750B-A1 system-level hardware interfa

Reset and hardware strapping timing76       NS9750B-A1 Datasheet 03/2006Reset and hardware strapping timingReset and hardware strapping AC ch

JTAG timingwww.digi.com       77JTAG timingJTAG AC characteristics are measured with 10pF, unless otherwise noted.Table 39 describes the values

Clock timing78       NS9750B-A1 Datasheet 03/2006Clock timingClock AC characteristics are measured with 10pF, unless otherwise noted.The next

Clock timingwww.digi.com       79System PLL reference clock timingTable 42 describes the values shown in the system PLL reference clock timing

Packaging80       NS9750B-A1 Datasheet 03/2006PackagingThe NS9750B-A1 dimensions and pinout are shown in the next two diagrams.Figure 7: NS97

Packagingwww.digi.com       81ABCDEFGHJKLMNPRTUVWYAAABACADAEAF234 561 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 260.635(1.625)1.270

Packaging82       NS9750B-A1 Datasheet 03/2006Figure 9 shows the layout of the NS9750B-A1, for use in setting up the board.For information ab

Product specificationswww.digi.com       83Product specificationsThese tables provide additional information about the NS9750B-A1.ROHS substanc

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System configurationwww.digi.com       5System configurationThe PLL and other system settings can be configured at powerup before the CPU boots